1. Field of the Invention
The present invention relates to logic analyzers and, more specifically, to logic analyzer data processing method, which decompresses test data obtained from test samples before storing in memory so that memory can store more test data.
2. Description of the Related Art
FIG. 1 illustrates the arrangement of a logic data analyzer according to the prior art. The logic analyzer comprises a logic analyzer main unit 10′. The logic analyzer main unit 10′ comprises detection devices 11′. Each detection device 11′ has multiple lead-wires 111′ and a clip 113′ at the end of each lead-wire 111′ for fastening to a respective pin of the test sample (for example, digital circuit). The detection devices 11′ detect high/low potential status of every pin of the test sample at a fixed time interval, and then transmit test data to a computer 16′ through a transmission interface (for example, USB interface, LPT interface, or the like) 15, enabling test data to be displayed on the display screen 161′ of the computer 16′. FIG. 2 is a system block diagram of the prior art logic data analyzer. The logic analyzer main unit 10′ comprises a control circuit 17′ and a memory (for example, SRAM) 18′. When received test data from the test sample 13′, the control circuit 17′ stores received test data in the memory 18′. When the memory space of the memory 18′ used up, the control circuit 17′ fetches storage test data from the memory 18′, and then transmits fetched test data to the computer 16′ through the transmission interface 15′ for display on the display screen 161′ of the computer 16′. Because the memory 18′ has a limited data storage space, it may not be able to store a complete series of test data. When the user debugging the digital circuit (test sample) based on an incomplete test result, the debugging work may take much time, or may be unable to proceed.
Therefore, it is desirable to provide a logic analyzer data processing method that eliminates the aforesaid problem.